Kunal Ghosh

Digital and Sign-off expert at VLSI System Design(VSD)

42
active courses
0
removed courses
Feb 2013
first content date
Oct 2024
last content date
Kunal Ghosh
105797
total students
14940
total reviews
4.29
average rating
146
total content length

Courses

VSDOpen2019 - VLSI online conference

VSDOpen2019 - VLSI online conference

92
students
5 hours
content
Oct 2019
updated
$19.99
VSDOpen2018 - First ever online VLSI conference

VSDOpen2018 - First ever online VLSI conference

3.1K
students
5.5 hours
content
Apr 2019
updated
$19.99
VSD - A complete guide to install open-source EDA tools

VSD - A complete guide to install open-source EDA tools

14.6K
students
3.5 hours
content
Aug 2020
updated
FREE
VSD - Mixed-signal RISC-V based SoC on FPGA

VSD - Mixed-signal RISC-V based SoC on FPGA

112
students
1.5 hours
content
Jul 2021
updated
$39.99
VSD Intern - 10-bit DAC design using eSim and Sky130

VSD Intern - 10-bit DAC design using eSim and Sky130

792
students
2 hours
content
Jun 2021
updated
$44.99
VSD Intern - DAC IP design using Sky130 PDKs - Part 3

VSD Intern - DAC IP design using Sky130 PDKs - Part 3

133
students
2.5 hours
content
May 2021
updated
$54.99
VSD Intern - DAC IP Design using Sky130 PDKs - Part 2

VSD Intern - DAC IP Design using Sky130 PDKs - Part 2

870
students
1.5 hours
content
May 2021
updated
$39.99
VSD Intern - DAC IP design using Sky130 PDKs - Part 1

VSD Intern - DAC IP design using Sky130 PDKs - Part 1

898
students
2 hours
content
May 2021
updated
$44.99
VSD Intern - Analog Comparator Design using Sky130

VSD Intern - Analog Comparator Design using Sky130

148
students
1 hour
content
Apr 2021
updated
$24.99
VSDOpen2020 - VLSI online conference

VSDOpen2020 - VLSI online conference

1.8K
students
5.5 hours
content
Mar 2021
updated
$44.99
VLSI - Essential concepts and detailed interview guide

VLSI - Essential concepts and detailed interview guide

12.9K
students
11.5 hours
content
Mar 2015
updated
$54.99
VSD - Clock Tree Synthesis - Part 1

VSD - Clock Tree Synthesis - Part 1

4.1K
students
4 hours
content
Jan 2017
updated
$64.99
VSD - Signal Integrity

VSD - Signal Integrity

3K
students
6.5 hours
content
Jan 2017
updated
$74.99
VSD - Physical Design Flow

VSD - Physical Design Flow

11.1K
students
6.5 hours
content
Feb 2023
updated
$64.99
VSD - Static Timing Analysis - I

VSD - Static Timing Analysis - I

7.6K
students
3.5 hours
content
Jan 2017
updated
$54.99
VSD - Circuit Design & SPICE Simulations - Part 2

VSD - Circuit Design & SPICE Simulations - Part 2

1.7K
students
3 hours
content
Feb 2017
updated
$64.99
VSD - Clock Tree Synthesis - Part 2

VSD - Clock Tree Synthesis - Part 2

3K
students
4 hours
content
Jan 2017
updated
$54.99
VSD - Custom Layout

VSD - Custom Layout

2.9K
students
4.5 hours
content
Jan 2017
updated
$54.99
VSD - Static Timing Analysis - II

VSD - Static Timing Analysis - II

5.2K
students
4 hours
content
Oct 2018
updated
$49.99
VSD - Static Timing Analysis (STA) Webinar

VSD - Static Timing Analysis (STA) Webinar

413
students
2.5 hours
content
May 2017
updated
$34.99
VSD - TCL programming - From novice to expert - Part 1

VSD - TCL programming - From novice to expert - Part 1

3.7K
students
4.5 hours
content
Dec 2017
updated
$44.99
VSD - TCL programming - From novice to expert - Part 2

VSD - TCL programming - From novice to expert - Part 2

2.3K
students
5 hours
content
Oct 2017
updated
$49.99
VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a

VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a

1.5K
students
2.5 hours
content
Jan 2019
updated
$39.99
VSD - Timing ECO (engineering change order) webinar

VSD - Timing ECO (engineering change order) webinar

1.1K
students
1.5 hours
content
Feb 2018
updated
$44.99
VSD - Physical Design Webinar using EDA tool 'Proton'

VSD - Physical Design Webinar using EDA tool 'Proton'

1.6K
students
3.5 hours
content
Jan 2018
updated
$34.99
VSD - Pipelining RISC-V with Transaction-Level Verilog

VSD - Pipelining RISC-V with Transaction-Level Verilog

741
students
3.5 hours
content
Feb 2018
updated
$34.99
VSD - Making the Raven chip: How to design a RISC-V SoC

VSD - Making the Raven chip: How to design a RISC-V SoC

1.2K
students
4.5 hours
content
Mar 2018
updated
$39.99
VSD - Machine Intelligence in EDA/CAD

VSD - Machine Intelligence in EDA/CAD

848
students
4 hours
content
Apr 2019
updated
$34.99
VSD - Library characterization and modelling - Part 2

VSD - Library characterization and modelling - Part 2

882
students
3.5 hours
content
May 2018
updated
$29.99
VSD - RTL Synthesis Q&A Webinar

VSD - RTL Synthesis Q&A Webinar

486
students
1.5 hours
content
May 2018
updated
$29.99
VSD - Distributed timing analysis within 100 lines code

VSD - Distributed timing analysis within 100 lines code

3.9K
students
2 hours
content
Jun 2018
updated
$19.99
VSD - SoC Design of the PicoRV32 RISCV micro-processor

VSD - SoC Design of the PicoRV32 RISCV micro-processor

673
students
4 hours
content
Jun 2018
updated
$39.99
VSD -  Embedded-UVM

VSD - Embedded-UVM

168
students
4 hours
content
Jun 2019
updated
$39.99
VSD - Circuit Design & SPICE Simulations - Part 1

VSD - Circuit Design & SPICE Simulations - Part 1

4.8K
students
4 hours
content
Jan 2017
updated
$44.99