VSD - Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this

4.50 (86 reviews)

Udemy

platform

English

language

Design Tools

What you will learn

Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform

Build their own verilog models for IP's using a simpler and powerful Verilog design environment

Why take this course?

Do you want to build just verilog models or high-quality verilog models in half the time?

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform

This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one.

Enjoy the webinar and Happy Learning....

Screenshots

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Reviews

Nguyen

January 7, 2023

It's mostly review for me since I have designing/verifying ASIC for decades now. I want to teach my son TL-Verilog.

Antoni

May 12, 2022

Casualmente buscando información en github acerca de RISC-V encontré una implementación en FPGA realizada en TL-Verilog ¿? Haciendo un poco de busqueda en internet encuentro un curso en EDX al cual me apunto (gratis) para entender un poco este lenguaje. Poco después, siendo usuario antiguo de udemy veo que también hay un curso (webminar) a un precio razonable y decido comprarlo. Lo he terminado y me ha parecido muy interesante pero me queda mucho trabajo por hacer y por aprender. Un gran viaje empieza con un simple paso. Gracias por el curso.

Shivam

April 7, 2020

TL-Verilog is definitely revolutionary, the way it has been designed is good enough to put it into good use right now, and integrate with existing Verilog based designs. And an even more interesting fact is that it is still evolving and expanding to other HDLs such as VHDL!

Sharan

January 17, 2020

No idea why they titled the course as 'Pipelining RISC-V'. This course is not about pipelining RISC-V at all. It could be any design block. It is mostly about TL-verilog and makerchip.com.

Jose

June 22, 2019

I really liked the presentation as it has the supporting material and is available for everyone, the use of the Makership web page is very valuable since it allows students to practice, compile and see the resulting waves for the code, it even tells you how much code lines it saves when compared to regular code, so overall I find the material of the course is really comprehensive.

Federico

June 6, 2018

Excellent presentation, examples and impressive tools. Perfect combination to offer so many concepts in just 3hs.

James

February 18, 2018

Provides a nice introduction of the highest level goals and objectives of the material, gives an overview and context, and then dives into Transaction Level (TL) Verilog. The TL Verilog concept is an extensible and useful addition on top of existing adopted infrastructure. I find it to be an efficient approach to pipeline design for flexible for quick implementation and re-timing. TL Verilog can sidestep a lot of the standard Verilog typing and unnecessary complexity, yet is compatible with well-known design approaches. This course provides a very accessible Makerchip environment so you can be up designing, simulating and validating quickly but at a simple yet meaningful level.

Gautham

February 17, 2018

Thank you for the awesome webinar. Going over the videos again helped me appreciate the advantages of TL-Verilog. I wish you guys all the best. I hope TL-Verilog takes off, like HLS seems to have recently. TL-Verilog definitely seems to simplify coding state machines and other digital logic in Verilog.

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