VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130

How to configure ope-source compiler OpenRAM for 130nm technology node

3.75 (21 reviews)
Udemy
platform
English
language
Design Tools
category
instructor
211
students
1 hour
content
Apr 2021
last update
$44.99
regular price

What you will learn

Configure open-source memory compiler OpenRAM for any memory size

SRAM custom cell design

Memory GDS/Lib/Lef file types

Description

This webinar aims at design of 1024x32 SRAM cell array (32Kbits or 4KB) with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.

Static Random-Access Memory (SRAM) has become a standard element of any Application Specific Integrated Circuit (ASIC), System-On-Chip (SoC), or other micro-architectures. For this wide variety of applications, SRAMs are configured using parameters like the word-length, bit lines, operating voltage, access time, and most importantly the technology node. The access time of an SRAM cell is the time require for a read or write operation of SRAM.

Manually configuring the SRAM for every change in parameter seems a slightly in-efficient and tedious task. Due to this reason, the memory compiler is used on a large scale, as it facilitates easy configuration and optimization of memory. OpenRAM, an open-source memory compiler is used for characterization and generation of SRAM designs.

This webinar mentioned multiple open-source circuit schematic design, layout design, SPICE simulations tools and memory compiler. The tools used are explained in detail. All the Skywater SKY130 PDKs related files are added to the repository mentioned in webinar, which can be used without installing the complete PDKs. To install or get other details of Skywater PDKs, it can be found in Skywater official website

Content

Introduction

Introduction to OpenRAM
Reasons to use OpenRAM and Sky130 technology

Environment Setup and custom cells description

OpenRAM environment setup
Bit-cells and sense amplifier details
Dummy & replica bit cells, D-flipflop and write driver details

OpenRAM technology setup

OpenRAM directory structure
GDS file creation
Tech file setup
Interconnect stack layer name and technology parameters
DRC rules and SPICE technology setup

Steps to execute OpenRAM

OpenRAM configuration script
Execute and review OpenRAM output files

Challenges, issues and fixes

Custom cells boundry box
GDS pins and tech layers
GDS DRC issues

Conclusion

Summary and conclusion

Screenshots

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Related Topics

3965020
udemy ID
4/7/2021
course created date
4/13/2021
course indexed date
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