VSD - Distributed timing analysis within 100 lines code

🎓 Webinar Invitation: Distributed Timing Analysis within 100 Lines of Code

📅 Date: 26th May 2018

---

Overview

In the world of chip design, timing analysis is a cornerstone that ensures electronic devices function correctly and efficiently. As designs grow in complexity, the traditional single-machine approach to timing analysis becomes less feasible due to its immense computational demands and time constraints. This webinar, led by the esteemed Tsung-Wei Huang, will explore the intricacies of Distributed Timing Analysis—a technique designed to tackle these challenges head-on.

---

Key Points of Discussion

• Local vs. Distributed Execution: Understanding the impact of executing set_multi_cpu_usage -localCpu 4 and set_multi_cpu_usage -localCpu 4 -numThreads 4 on your EDA timing shell.
• Distributed Computing: Curiosity about how jobs are distributed across multiple machines, especially when there's a mismatch between the number of jobs and available machines.
• Timing Engine Architecture: Insights into how a timing engine handles distributed analysis and the complexities involved.
• Distributed Timing Analysis: The importance of this approach to accelerate timing closure by considering various conditions and corner cases.
• DTCraft: A high-performance cluster computing engine that enables efficient distribution of timing analysis tasks within 100 lines of code.

---

Agenda

• Introduction to Distributed Timing Analysis: Why it's necessary and how it differs from traditional methods.
  • What happens when you adjust your local CPU usage in the EDA timing shell?
• Understanding Distributed Computing in STA: How the architecture of a timing engine can be optimized for distributed computing.
• DTCraft: A Cluster Computing Solution: An overview of DTCraft and its role in streamlining the timing analysis process.
• Labs and Hands-On Learning: Opportunities to apply what you've learned in real-world scenarios.
• Framework Understanding: Gaining a deeper insight into the framework that enables distributed timing analysis.

---

Why Attend?

Are you curious about the inner workings of timing engines and how to optimize them for better performance? Do you want to master the art of distributed timing analysis and become an expert in Signal Timing Analysis (STA)? Enrolling in this webinar is your chance to:

• Discover Answers: Learn from Tsung-Wei Huang, the architect behind a popular opensource STA tool, Opentimer.
• Enhance Your Skills: Become a more proficient STA engineer or lead by understanding the complexities and solutions in chip design.
• Practical Knowledge: Engage in labs and hands-on exercises to solidify your understanding of the framework and its application.

---

Speaker Profile: Tsung-Wei Huang 🎓

Tsung-Wei Huang is not just an educator but also a visionary in the field of Electrical and Computer Engineering. As a Research Assistant Professor at the University of Illinois at Urbana-Champaign, his expertise and innovative research have led to significant advancements in the field. With a PhD from the same institution, Tsung-Wei has contributed to the industry with 2 patents and over 30 conference and journal paper publications. His knowledge and experience are invaluable for anyone looking to deepen their understanding of distributed timing analysis in chip design.

---

Join us for this insightful webinar and take a step towards mastering the complexities of timing analysis in chip design. Don't miss out on the opportunity to learn from a leader in the field and enhance your career as an STA engineer or lead. 🌟

Enroll now and embark on a journey to become an expert in distributed timing analysis!