VSDOpen2018 - First ever online VLSI conference

🚀 VSDOpen2018: The Premier Online VLSI Conference 🌐

Dive into the world of cutting-edge semiconductor design with VSDOpen2018, an immersive and interactive online conference that took place on 27th October, 2018. This comprehensive six-hour program focuses on leveraging open source hardware tools to push the boundaries of IC design, from the drawing board to the silicon wafer, with a spotlight on developing IP that meets the highest standards of performance, area, and power (PPA).

What to Expect:

🔍 Core Topics Covered:

• Front-end Open-Source EDA Tool Flows for IC Design and Verification: Mastering the foundational tools for modern semiconductor design.
• Clock Tree Synthesis & Optimization: Learn how to optimize clock trees in digital ICs for superior performance.
• Floorplanning Digital ICs: Understand the art of floorplanning to achieve the best area utilization.
• Place and Route of Digital ICs: Explore techniques for effective placement and routing that balance PPA requirements.
• Standard Cell Layout & Characterization: Discover methods for creating compact standard cells that offer high performance with minimal routing resources.
• Machine Learning in EDA: Get insight into how machine learning is revolutionizing the field of Electronic Design Automation (EDA).

🎤 Memorable Keynotes:

• "A New Golden Age in Computer Architecture" by Prof. David Patterson, a pioneer in computer architecture and winner of the Turing Award.
• "Professional Growth with ACM SIGDA" by Prof. Sharon Hu, an expert in VLSI CAD and education.
• "Applying Open Community Innovation to Hardware Product Creation" by Mohamed Kaseem, co-founder of Fusion Chambers.

📊 Papers on RISC-V and OpenSource EDA:

• TAU 2019 Contest Announcement by George Chen from Intel.
• Padframe Generator for Qflow by Phillip Guhring from Vienna, Austria.
• PNR of Digital Core IC using Cloud-based EDA Tools by Anand Rajgopalan from Mumbai University.
• Coverage-Driven Functional Verification on RISC-V Cores by Lavanya J., Anmol Sahoo, and Paul George from IIT Madras.
• Rapid Physical IC Implementation and Integration using efabless Platform by Alberto Gomez Saiz from Imperial College London.
• Introduction to TL-Verilog by Steve Hoover, CEO of Redwood EDA.
• Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator by Akos Hadnagy from TU Delft.
• Top-Down Transaction Level Design with TL-Verilog by Ahmed Salman from Alexandria University.

Join us as we explore the synergy of open source tools and EDA, pushing the envelope in IC design and paving the way for the future of hardware innovation. 🛠️🚀

Don't miss out on this opportunity to learn from industry leaders, engage with peers, and stay ahead in the fast-paced world of VLSI! Register now and be part of VSDOpen2018 - where open source meets the forefront of semiconductor design.