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VSD - Making the Raven chip: How to design a RISC-V SoC

Building a chip is like building a city...

Course Overview:

Are you ready to embark on an intellectual odyssey that parallels the grand endeavor of urban development? In this course, we'll journey through the intricate world of System-on-Chip (SoC) design, specifically focusing on the RISC-V architecture. Join us as Kunal Ghosh guides you through the process of creating a chip from scratch, drawing parallels with the complex task of building a bustling metropolis.

What You'll Learn:

• 🏙️ Understanding Chip Planning: Delve into the strategic decisions that shape an SoC, including analog and digital peripherals, memory mapping, and top-level connections like pads, level shifters, and GPIOs.

• 🤔 GPIO Conundrum: Explore the fascinating world of General Purpose Input/Output (GPIO) pins and how they serve as the interface between your SoC and the external environment.

• 📚 Memory Mapping Mastery: Learn the essentials of memory mapping within an SoC, and understand how different components are addressed and accessed.

• 🔧 Analog Peripheral Integration: Gain insights into integrating critical analog components like ADCs and DACs, and the role they play in your SoC's functionality.

• 🤖 Digital Peripherals and Configuration: Discover how to design and configure digital peripherals such as UARTs and flash controllers to support your SoC's communication and storage needs.

• 📝 Writing Your Own Datasheet: Master the art of documenting your SoC, creating a datasheet that captures all the critical details of your design.

Why This Course?

• Expert Guidance: Learn from industry experts like Kunal Ghosh, Tim Edwards, and Mohamed Kassem through their insights and experiences.

• Real-World Application: Transition from theoretical knowledge to practical skills by designing your own SoC.

• Stay Ahead of the Curve: Semiconductor technology is evolving rapidly; this course ensures you're at the forefront with cutting-edge knowledge.

Who Is This For?

This webinar is tailored for:

• Electrical Engineering Students and Professionals
• Embedded Systems Designers
• Hardware Engineers looking to expand their expertise in SoC design
• Anyone fascinated by the inner workings of computer chips and eager to learn how to design them from scratch.

What's Included?

• Access to a comprehensive webinar recording conducted on Mar 10, 2018.

• Exclusive insights into designing a RISC-V based SoC with a focus on modularity and scalability.

• A wealth of resources to support your learning journey.

Enroll Now and Join Us!

Embark on this transformative learning experience, and unlock the potential of becoming a Core SoC designer. Enroll today and start crafting your own datasheet, just like a blueprint for a new city. This is your chance to rise above and lead the semiconductor revolution.

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Happy to welcome you to this enlightening journey into chip design. I look forward to seeing you at the webinar where we'll dive deep into the fascinating world of SoCs. Keep learning, keep innovating, and let's create the future together! 🚀

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Note: This course is designed for individuals with a background in electronics or computer engineering who have a foundational understanding of digital logic design and are looking to expand their knowledge into SoC design.

🔑 Course Overview:

This course provides an in-depth understanding of System-on-Chip (SoC) Integrated Platform (IP) design, with a focus on the flow from concept to verification. It utilizes efabless, an open-source community platform that offers a range of design sources, simulation, synthesis, and routing tools for free.

Pros:

• Comprehensive Collection of Resources: The course offers access to a wide array of design source codes, simulations, synthesis, and routing tools available on the efabless platform.
• Real-World Examples: It includes a detailed example of designing a small System-on-Chip (PicoRV32) using an actual X-Fab 180nm model, complete with Verilog source code and guidance on creating a test bench for RTL development.
• RTL Development Insight: The course is particularly beneficial for those with front-end experience looking to understand the back-end development process from RTL to gate design and layout with standard cells.
• Quality Content: The playback, video quality, and content are of a high standard, though some learners may find the need to adjust playback speed for comprehension.

Cons:

• Remote Desktop Editing Challenges: There is no option for local source code editing, and the remote desktop can be high-latency when editing source code.
• Synthesis and Routing Process Documentation: While there is less emphasis on synthesis and routing processes within the webinar, detailed documentation is provided to follow up on these aspects.
• Outdated Content: Some modules are considered older, and the efabless interfaces have changed since the course was created, which may cause some confusion for learners.
• Pacing and Accessibility: The presenter moves through the presentation quickly, and the course is based on an outdated version of the efabless website. Some learners found it necessary to slow down the playback speed or use captions to understand the content fully.

Additional Feedback:

• Practical Discussion Needed: Learners suggest that practical discussions alongside design discussions, such as Verilog blocks for components like an ALU or control circuit, and a deeper dive into the Instruction Set Architecture (ISA) of chips like Raven, would be highly beneficial.
• Course Interface Improvement: Some learners pointed out the need for updated interfaces that are more intuitive and aligned with the current design of efabless.

Final Verdict:

The course is a valuable resource for those looking to gain insight into the full spectrum of SoC IP design, particularly for individuals with front-end experience who wish to explore back-end development processes. While there are some drawbacks related to outdated content and pacing issues, the comprehensive collection of resources and practical examples make it a solid learning tool. With some improvements to the course content and interface, this course could be an even more effective learning experience for aspiring SoC designers.

Global Course Rating: 3.60/5