VSD - Static Timing Analysis - I
VLSI - Essential timing checks
What you will learn
Understand various STA checks for timing closure
Able to do a quality analysis for real designs
Know-how on how real STA works in industries, something which you will not find in any books
Step-by-step and structured timing analysis
Description
Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.
Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations
The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details
Hope you enjoy learning this course in the same way we enjoyed making them.
Happy Learning !!
Content
Introduction and agenda
First things first - Introduction to timing graph
Clk-to-q delay, library setup, hold time and jitter
Textual timing reports and hold analysis
On-chip variation
OCV timing and pessimism removal
Conclusion
Screenshots
Reviews
Coupons
Submit by | Date | Coupon Code | Discount | Emitted/Used | Status |
---|---|---|---|---|---|
- | 2/25/2020 | 950BD14F28E95B8FA1DE | 89% OFF | expired |