Kumar Khandagle

FPGA Developer Lead @ FinTech

24
active courses
7
removed courses
Mar 2020
first content date
Feb 2024
last content date
Kumar Khandagle
46305
total students
6774
total reviews
4.53
average rating
278
total content length

Courses

Communication Series P1 : UART, SPI and I2C in Verilog

Communication Series P1 : UART, SPI and I2C in Verilog

393
students
7.5 hours
content
Feb 2024
updated
$84.99
Building Processor  with VHDL from Scratch

Building Processor with VHDL from Scratch

92
students
3.5 hours
content
Jun 2023
updated
$74.99
Building a Processor with Verilog HDL from Scratch

Building a Processor with Verilog HDL from Scratch

556
students
3 hours
content
Jun 2023
updated
$54.99
UVM for Verification Part 2 : Projects

UVM for Verification Part 2 : Projects

3.1K
students
8.5 hours
content
Jan 2024
updated
$74.99
UVM for Verification Part 1 : Fundamentals

UVM for Verification Part 1 : Fundamentals

4.4K
students
11 hours
content
Aug 2023
updated
$79.99
SystemVerilog for Verification Part 2 : Projects

SystemVerilog for Verification Part 2 : Projects

5.3K
students
12 hours
content
Jan 2024
updated
$74.99
SystemVerilog for Verification Part 1: Fundamentals

SystemVerilog for Verification Part 1: Fundamentals

8.3K
students
14.5 hours
content
Dec 2022
updated
$79.99
Embedded System Design with Microblaze and Vitis IDE

Embedded System Design with Microblaze and Vitis IDE

318
students
8 hours
content
Jan 2022
updated
$59.99
Embedded System Design with Xilinx Microblaze and SDK

Embedded System Design with Xilinx Microblaze and SDK

241
students
7.5 hours
content
Dec 2021
updated
$69.99
SystemVerilog Functional Coverage for Newbie

SystemVerilog Functional Coverage for Newbie

1.3K
students
7.5 hours
content
Aug 2023
updated
$79.99
SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

388
students
19.5 hours
content
Mar 2023
updated
$79.99
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

7.3K
students
16.5 hours
content
Jan 2024
updated
$89.99
Writing SystemVerilog Testbenches for Newbie

Writing SystemVerilog Testbenches for Newbie

2.7K
students
8.5 hours
content
Jun 2022
updated
$79.99
VHDL for an FPGA Engineer with Vivado Design Suite

VHDL for an FPGA Engineer with Vivado Design Suite

1.7K
students
19.5 hours
content
Jun 2023
updated
$69.99
Embedded System Design with Xilinx ZYNQ SoC and SDK

Embedded System Design with Xilinx ZYNQ SoC and SDK

618
students
12.5 hours
content
Nov 2022
updated
$59.99
UVM Testbenches for Newbie

UVM Testbenches for Newbie

3K
students
4.5 hours
content
Nov 2022
updated
$79.99
Verilog HDL Interview Preparation Guide

Verilog HDL Interview Preparation Guide

485
students
6.5 hours
content
Apr 2021
updated
$69.99
Synthesizable SystemVerilog for an FPGA/RTL Engineer

Synthesizable SystemVerilog for an FPGA/RTL Engineer

409
students
9 hours
content
Jun 2022
updated
$59.99
Learning UVM Testbench with Xilinx Vivado 2020

Learning UVM Testbench with Xilinx Vivado 2020

479
students
11 hours
content
Mar 2022
updated
$64.99
SystemVerilog Assertions (SVA) for Newbie

SystemVerilog Assertions (SVA) for Newbie

1.6K
students
10 hours
content
May 2023
updated
$79.99