Kumar Khandagle

Trainer @ NAMASTE FPGA
4.51 (10520 reviews)
26
active courses
9
removed courses
Mar 2020
first content date
Apr 2025
last content date
Kumar Khandagle
73876
total students
10520
total reviews
4.51
average rating
287
total content length
Courses
Building SDRAM Controller in Verilog from Scratch

Building SDRAM Controller in Verilog from Scratch

18
students
5 hours
content
Apr 2025
updated
$44.99
Verification Series Part 5: UVM RAL Essentials

Verification Series Part 5: UVM RAL Essentials

3K
students
7 hours
content
Jan 2025
updated
$79.99
PyUVM Series Part 1 : Python Fundamentals

PyUVM Series Part 1 : Python Fundamentals

77
students
4 hours
content
Jul 2024
updated
$34.99
PyUVM Series Part 2 : COCOTB fundamentals

PyUVM Series Part 2 : COCOTB fundamentals

112
students
4 hours
content
Jan 2025
updated
$54.99
Resume Essentials for VLSI Internships and Entry-Level Jobs

Resume Essentials for VLSI Internships and Entry-Level Jobs

1.7K
students
1 hour
content
Jun 2024
updated
FREE
Verification Series Part 4: UVM Projects

Verification Series Part 4: UVM Projects

5.3K
students
8.5 hours
content
Mar 2025
updated
$74.99
Building a Processor with Verilog HDL from Scratch

Building a Processor with Verilog HDL from Scratch

1.4K
students
3 hours
content
Oct 2024
updated
$54.99
Verification Series Part 3: UVM Essentials

Verification Series Part 3: UVM Essentials

7.7K
students
11 hours
content
Jan 2025
updated
$79.99
Verification Series Part 2: Hands-On SystemVerilog Projects

Verification Series Part 2: Hands-On SystemVerilog Projects

8.1K
students
8 hours
content
Jan 2025
updated
$74.99
Embedded System Design with Xilinx Zynq SoC and Vitis IDE

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

865
students
11 hours
content
Sep 2022
updated
$59.99
Verification Series Part 1: SystemVerilog Essentials

Verification Series Part 1: SystemVerilog Essentials

13.5K
students
14.5 hours
content
Feb 2025
updated
$79.99
Embedded System Design with Microblaze and Vitis IDE

Embedded System Design with Microblaze and Vitis IDE

528
students
8 hours
content
Jan 2022
updated
$59.99
Verification Series Part 7:SystemVerilog Functional Coverage

Verification Series Part 7:SystemVerilog Functional Coverage

2.3K
students
7.5 hours
content
Jan 2025
updated
$74.99
SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

583
students
19.5 hours
content
Mar 2023
updated
$74.99
Verification Series Part 6 : SystemVerilog Assertions Basics

Verification Series Part 6 : SystemVerilog Assertions Basics

2.8K
students
10 hours
content
Nov 2024
updated
$79.99
Learning UVM Testbench with Xilinx Vivado 2020

Learning UVM Testbench with Xilinx Vivado 2020

572
students
11 hours
content
Mar 2022
updated
$59.99
Learning SystemVerilog Testbenches with Xilinx Vivado 2020

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

682
students
9 hours
content
Sep 2021
updated
$59.99
UVM Testbenches for Newbie

UVM Testbenches for Newbie

3.7K
students
4.5 hours
content
Nov 2022
updated
$69.99
Embedded System Design with Xilinx ZYNQ SoC and SDK

Embedded System Design with Xilinx ZYNQ SoC and SDK

791
students
12.5 hours
content
Nov 2022
updated
$59.99
Embedded System Design with Xilinx Microblaze and SDK

Embedded System Design with Xilinx Microblaze and SDK

283
students
7.5 hours
content
Jan 2022
updated
$64.99
Building Custom AXI Interface Peripherals for ZYNQ Devices

Building Custom AXI Interface Peripherals for ZYNQ Devices

624
students
7 hours
content
Nov 2021
updated
$49.99
VHDL for an FPGA Engineer with Vivado Design Suite

VHDL for an FPGA Engineer with Vivado Design Suite

2K
students
19.5 hours
content
Jun 2023
updated
$69.99
Writing SystemVerilog Testbenches for Newbie

Writing SystemVerilog Testbenches for Newbie

3.2K
students
8.5 hours
content
Jun 2022
updated
$74.99
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

10.4K
students
16.5 hours
content
Jan 2025
updated
$84.99
Building Processor with VHDL from Scratch

Building Processor with VHDL from Scratch

151
students
3.5 hours
content
Jun 2023
updated
$74.99
Communication Series P1 : UART, SPI and I2C in Verilog

Communication Series P1 : UART, SPI and I2C in Verilog

1.9K
students
7.5 hours
content
Jun 2024
updated
$69.99
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