Kumar Khandagle
FPGA Developer Lead @ FinTech
24
active courses
7
removed courses
Mar 2020
first content date
Feb 2024
last content date
46305
total students
6774
total reviews
4.53
average rating
278
total content length
Courses
Communication Series P1 : UART, SPI and I2C in Verilog
393
students
7.5 hours
content
Feb 2024
updated
$84.99
UVM for Verification Part 3:Register Abstraction Layer (RAL)
1.5K
students
7 hours
content
Mar 2023
updated
$79.99
SystemVerilog for Verification Part 1: Fundamentals
8.3K
students
14.5 hours
content
Dec 2022
updated
$79.99
Embedded System Design with Xilinx Zynq SoC and Vitis IDE
508
students
11 hours
content
Sep 2022
updated
$59.99
Embedded System Design with Xilinx Microblaze and SDK
241
students
7.5 hours
content
Dec 2021
updated
$69.99
SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1
388
students
19.5 hours
content
Mar 2023
updated
$79.99
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite
7.3K
students
16.5 hours
content
Jan 2024
updated
$89.99
VHDL for an FPGA Engineer with Vivado Design Suite
1.7K
students
19.5 hours
content
Jun 2023
updated
$69.99
Building Custom AXI Interface Peripherals for ZYNQ Devices
541
students
7 hours
content
Nov 2021
updated
$49.99
Embedded System Design with Xilinx ZYNQ SoC and SDK
618
students
12.5 hours
content
Nov 2022
updated
$59.99
Learning SystemVerilog Testbenches with Xilinx Vivado 2020
544
students
9 hours
content
Sep 2021
updated
$64.99