SystemVerilog for Verification Part 2 : Projects

Verification of Common Peripherals, Memories, and Bus Protocol

4.42 (515 reviews)
Udemy
platform
English
language
Hardware
category
instructor
SystemVerilog for Verification Part 2 : Projects
5,281
students
12 hours
content
Jan 2024
last update
$74.99
regular price

What you will learn

Verification of Memories viz. FIFO

Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone

Verification of Interface Communication Protocols viz. SPI, UART, I2C

Verification of Simple Compinational Block viz. Adder

Verification of Simple Sequential Block viz. Data Flipflop

Description

The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times.

SystemVerilog has become the primary choice of verification engineers to perform verification of complex RTL's. SystemVerilog object-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimum effort.

Each complex system in FPGAs is built with the help of multiple subsystems. These subsystems can be either simple sequential components / simple combinational components / data communication protocols RTL / bus protocol RTL.

Once we understand strategies to perform verification of the common subsystems, you can easily perform verification of any complex system with the same logic.

Our objective for the course will be to build logic with the help of the fundamentals discussed in the first part of the course to perform verification of these common subsystems. We start our course by performing verification of data flipflops and FIFOs, then proceed to verification of common data communication protocols, viz., SPI, UART, and I2C. Finally, we will perform the verification of bus protocols, viz., ABP, AHB, AXI, and Whishbone protocol.

Content

Sequential Design Block: Verification of FIFO

Understanding Design P1
Understanding Design P2
Code
Transaction Class P1
Transaction Class P2
Transaction Class P3
Code
Generator Class
Driver Class P1
Driver Class P2
Driver Class P3
Code
Monitor Class
Code
Scoreboard Class P1
Scoreboard Class P2
Code
Environment Class
Code
Testbench Top
Complete Code

Sequential Design Block: Verification of D-FF

Understanding Design
Transaction Class
Generator Class
Driver Class
Monitor and Scoreboard Class
Testbench Top P1
Testbench Top P2
Complete Code

Communication Protocol: Verification of Serial Peripheral Interface (SPI)

Understanding SPI P1
Understanding SPI P2
Understanding Design P1
Understanding Design P2
Adding Interface
Transaction Class
Generator Class
Driver Class P1
Driver Class P2
Adding Testbench Top
Monitor Class
Adding Testbench Top
Scoreboard Class
Environment Class
Testbench Top
Code

Communication Protocol: Verification of UART

Understanding Protocol
Understanding Design P1
Understanding Design P2
Understanding Design P3
Transaction Class
Generator Class
Driver Class P1
Driver Class P2
Monitor Class
Scoreboard Class
Environment Class
Testbench Top
Design Code
Testbench Code

Communication Protocol: Verification of I2C(Inter-Integrated Circuit)

Understanding I2C protocol P1
Understanding I2C protocol P2
Understanding I2C protocol P3
System Flowchart
Understanding System Top
Understanding Design I2c Controller P1
Understanding Design I2c Controller P2
Understanding Design I2c Controller P3
Understanding Design I2c Controller P4
Understanding Design I2c Controller P5
Understanding I2C memory
Adding Interface
Transaction Class
Generator Class
Driver Class
Monitor Class
Scoreboard Class
Testbench Top
Code

Bus Protocol: Verification of APB_RAM

Understanding Advanced Peripheral Bus Signals
Understanding APB Transactions P1
Understanding APB Transactions P2
Understanding Design
Code
Transaction Class P1
Transaction Class P2
Code
Generator Class
Code
Adding Interface
Driver Class P1
Driver Class P2
Code
Monitor Class
Code
Scoreboard Class
Code
Environment and Testbench Top
Code
Complete Code

Bus Protocol: Verification of AXI Memory

Understanding AXI Channels
Understanding Write address Signals
Understanding Write Data Signals
Understanding Read Signals
Understanding Design P1
Understanding Design P2
Understanding Burst Mode P1
Understanding Burst Mode P2
Summary
Implementing FIXED Mode
Implementing INCR Mode
Implementing WRAP Mode
Understanding Design P3
Understanding Design P4
Understanding Design P5
Understanding Design P6
Transaction Class
Generator Class
Driver Class P1
Driver Class P2
Driver Class P3
Driver Class P4
Monitor Class
Scoreboard Class
Testbench Top
Code

Bus Protocol: Verification of AHB Memory

Understanding AHB Signals P1
Understanding AHB Signals P2
Understanding Design P1
Understanding Design P2
Understanding Design P3
Understanding Design P4
Understanding Design P5
Transaction Class
Generator Class
Driver Class P1
Driver Class P2
Driver Class P3
Monitor Class
Scoreboard Class
Verifying different Burst Modes P1
Verifying different Burst Modes P2
Design Code
Testbench Code

Bus Protocol: Verification of Whishbone Memory

Understanding Protocol
Understanding Design
Transaction Class
Generator Class
Driver Class
Monitor Class
Scoreboard Class
Testbench Top
Design Code
Testbench Code

Reviews

Gadamchetty
September 18, 2023
Excellent course and teaching really amazing very good course for begineers who want to do basic projects in system verilog
George
August 14, 2023
The class shows examples of simple TB cases and builds on that. I needed this as I never developed complete TBs. I wish the instructor does not use "Right" and "OK" several times in a sentence. It is not easy to concentrate on the subject.
Raveen
June 29, 2023
The way of teaching is impressive and the way the author delivers the small small details it's very impressive.
Loc
May 26, 2023
Very informative and thorough explanation of each project and associated classes. Thank you very much.
Kirtikesh
May 17, 2023
The instructor really tried his best but the complex bus protocols are still difficult to understand. Still a good course for being more familiar with the verification environment.
YAYAVARAM
January 21, 2023
So far its fine ...gong great.... Just a friendly adviceis ,the trainer can avoid using some of the mannerisms like "right" repatedly ...of course it will no where affect the qualty...
rainbow
January 7, 2023
Great approach to teach starting from simple projects to difficult one thereby making the audience ready to receive the complexity gradually. Great content. Great examples. Awesome. Great explanations Unable to fault anything
Ashish
October 28, 2022
course is good for the better understanding of the system verilog but it could be more precise about the particular code most often the word "WHY" struck in our mind and there is no answer about it in the but nevermind course is bit good and systematic too i have done part1 and now part2
Anweshan
October 7, 2022
Nicely explained everything (I also did the part 1) But in prerequisites you should add - C programming fundamentals - C++ - OOPs I think I would have really struggled to understand if I hadn't studied these before
Moreshwar
September 19, 2022
Overall The course starts well and at good. working along with the instructor helps understand it better. However, AXI Memory and ADB Memory could be improved. I found below issues: Some lectures like lecture 111 and lecture 112 are long. The instructor is attempting to explain the pre-written code and the code is lot big file and editor is Vivado (likely). There is a lot of movement in the editor while explaining the code and i saw movements from lines 800+ to 400+ and then showing the flowcharts. It's easy to lose focus and get distracted but that may be my case only. Splitting the lectures into smaller parts would have helped and having the flowchart along the code would have certainly helped. Other than that, having so many variables in the code makes it more difficult to follow with the movement up and down between two functions e.g.to wrap_boundary A note of caution to further course takers, keep the flowcharts etc handy when doing AXI Memory, really difficult to keep track otherwise Also, AXI and AHB are commonly used and therefore a little slower pacing would have helped definitely. Now, I will have to look at AHB and AXI all over again to understand what the instructor said so two sections again :( Also want to add on subtitles as I don't see many reviews: Please clean them. I dont have idiot playground IDE and no chance of straub in Wishbone memory for example.
Hickmat
September 18, 2022
the advanced protocols are very hard to understand from the videos alone, without providing the related notes its almost impossible for students to follow the steps and keep track on the explanations yet the instructor did great effort. without previous knowledge of the protocols it will be very hard to understand because the videos alone are not enough in my opinion

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4574206
udemy ID
2/28/2022
course created date
5/9/2022
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