Simple AXI bus Design using Verilog HDL

AXI in easy understand

3.35 (10 reviews)
Udemy
platform
English
language
Hardware
category
Surender Reddy T
instructor
Simple AXI bus Design using Verilog HDL
43
students
1 hour
content
Dec 2023
last update
$19.99
regular price

What you will learn

Concept of AMBA bus protocol

Concept of AXI Bus

Design and implementation of AXI bus using Verilog HDL

Verification of AXI bus

5724684
udemy ID
12/22/2023
course created date
12/29/2023
course indexed date
Bot
course submited by
Simple AXI bus Design using Verilog HDL -