Surender Reddy T

Developer

6
active courses
0
removed courses
Aug 2020
first content date
Aug 2024
last content date
Surender Reddy T
2046
total students
426
total reviews
4.15
average rating
20
total content length

Courses

RISC processor with own Instruction Set Architecture (ISA)

RISC processor with own Instruction Set Architecture (ISA)

124
students
1.5 hours
content
Oct 2021
updated
$44.99
Step by step hands-on design of UART using Verilog HDL

Step by step hands-on design of UART using Verilog HDL

216
students
3 hours
content
Jul 2022
updated
$39.99
Simple FIFO Design and Simulation using Verilog HDL

Simple FIFO Design and Simulation using Verilog HDL

226
students
1 hour
content
Jun 2021
updated
$24.99
Complete Verilog HDL programming with Examples and Projects

Complete Verilog HDL programming with Examples and Projects

1.3K
students
8 hours
content
Jun 2023
updated
$49.99
Simple AXI bus Design using Verilog HDL

Simple AXI bus Design using Verilog HDL

43
students
1 hour
content
Dec 2023
updated
$19.99
Python Programming Hands-on

Python Programming Hands-on

159
students
4.5 hours
content
Aug 2024
updated
$19.99

Related Topics

Instruction Set Architecture
Verilog HDL Programming