Xilinx Vivado Essentials for the Logic Designer

Getting started with Vivado and the SDK

4.50 (69 reviews)

Udemy

platform

English

language

Development Tools

What you will learn

Getting started designing FPGAs with Xilinx Vivado Design Tools

Why take this course?

Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device. This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl. Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design. We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.

Screenshots

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Reviews

Karl

November 26, 2022

This course is very well written and extremely helpful. Scott is readily available for any questions and help that you will need. The best part is that he is doing it because he wants to help anyone willing to learn about FPGAs!!

James

November 7, 2022

Good selection and thorough coverage of topics for basic design on the Xilinx Zynq platform using Vivado/Vitis.

Rolf

December 18, 2020

Good Overview on handling standard procedures with Vivado. When it comes to Vitis and the SDK to run SW on the processor core, the explanations are reduce to "click here and here" which is ok for an overview but I would have liked to get a more deeper explanation on the interworking of Vivado and Vitis. I understand that a deeper explanation of how to run SW on the FPGA Processor and how to interface to GPIOs, IRQs etc would be worth a whole course on udemy.