Video Processing with FPGA

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

4.30 (80 reviews)


4.5 hours


Jul 2020

Last Update
Regular Price

What you will learn

Implement different Computer Vision algorithm for Video Processing

Creating IP from the VIVADO High Level Synthesis

IP integration and configuration with Xilinx VIVADO

Xilinx SDK Application Development

Migrating the OpenCV algorithm on XfOpenCV

Simulating & Generating XfOpenCV codes in the VIVADO HLS

Integrating TPG, VDMA and Writing application for this blocks


This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

After Completing this course you will be able to:

  1. Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

  2. Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

  3. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

  4. Migrating the OpenCV algorithm into XfOpenCV


Video Processing with FPGA
Video Processing with FPGA
Video Processing with FPGA
Video Processing with FPGA


Introduction to HLS, VIVADO IP Integrator and SDK

VIVADO High Level Synthesis [HLS] Overview

Overview of Xilinx VIVADO , IP and Zynq FPGA Architecture

Section 1_2 TPG,VDMA and Video Processing Platform Development

TPG Overview

Lab 1 Part I: TPG Project Development LAB on VIVADO

Lab 1 Part II: TPG Development [SDK Configuration with Zynq PS]

Demo: TPG Implementation on ZedBoard FPGA

TPG and VDMA Overview

Lab 2 Part I: TPG & VDMA- VIVADO IP Block Design

Lab 2 Part II: TPG & VDMA- SDK Application Development

Demo: TPG & VDMA Project Implementation on ZedBoard

Section 2_1 Sobel Edge Detection with FPGA

Sobel Edge Detection-HLS & OpenCV Algorithm

Lab 1 Sobel IP Design on VIVADO HLS

Lab 2 VIVADO IP integration of Sobel Edge IP on Streaming Mode

Sobel Edge Demonstration on Zybo FPGA

Section 2_2 Dilation & Histogram Equalize implementation on HLS

Histogram Equalize Overview

Section 3: Fast Corner & Harrish Corner Detection

Fast Corner Detection Algorithm Overview

Lab 31: Fast Corner Algorithm HLS Synthesis, C Simulation & Implementation

Harrish Corner Overview and Lab Intro

Porting xfOpenCV into HLS

Porting xfOpenCV Harrish Corner into HLS

Bonus Section

What Next?

Reference Links


Isaac28 August 2020

Still hard to comprehend, but it is diving into directly relevant needed material to create FPGA Block Diagrams in the work environment.

Lorenzo26 June 2020

Very good overview about the technologies on the image processing on FPGA world with hands on exercises.

Giannis5 December 2019

Besides pronunciation, i learned some really good stuff that can't find anywhere and they are helpful.

Yash23 June 2019

Great course on FPGA based image processing. Really supportive instructor. I am very much thankful to Krishna sir for clearing my doubts so helpfully. I recommend this course to everyone

Gourav7 February 2019

First of all,this course is so well organized and give all necessary information regarding video processing and how we can enhance quality using harrish corner and sobel algoritham. Apart from that its value for money course ,all materials links are shown and provided ,for further work.


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