Xilinx VIVADO Beginner Course for FPGA Development in VHDL

Learn how to Create VHDL Design,Simulation Testbench & Implementation with Xilinx VIVADO & FPGA: from Basic to Advanced.

4.15 (51 reviews)
Udemy
platform
English
language
Hardware
category
413
students
5 hours
content
Jan 2019
last update
$54.99
regular price

What you will learn

Idea of VHDL Programming , VIVADO Design Methodology and Designing/Implementing Design in Zynq FPGA-ZedBoard

Use fundamental VHDL constructs to create simple designs. Understanding the Conditional Statements in VHDL.

Design Simulation testbench on VHDL and simulating the designs.

Design with structural design methodology on VHDL.

Designing Decoder, Adder, Register and Counter in VHDL and Implementing in ZedBoard

Implementing State Machine in VHDL; Designing/Implementing Sequence Detector

Description

"Learn VIVADO Development from Basic to Intermediate Level!!!"

This Course is of VHDL Programming from Basic (logic gate design) to Advance Design (Structural Design and State Machine Design). After completing the course student will get idea of VHDL programming design methodology, VIVADO Design Flow, Zynq Architecture, Creating Simulation Testbench, Conditional Statements, Combinational Circuit Design with VHDl, Sequential Circuit Design, Structural Design in VHDL and State Machine Design in VHDL. 

In each section we have included Lab session on VIVADO which have been implemented on Zynq Board (i.e ZedBoard) FPGA, so Student will get complete design skill on VHDL with VIVADO.

You guys can Learn the course while using ISE Design Suit.While VIVADO is successor of ISE so this Course and VHDL Design Methodology is same for ISE based design so do not scare about VIVADO because of it just a latest version of Design tool than ISE.

The Top Level Outlines of the Course is:

  1. Basic Digital Design with VHDL and VIVADO Tool

  2. Creating Testbench on VHDL and Simulating with VIVADO Tool

  3. Combinational  Circuit Design in VHDL: Decoder Design,

  4. Sequential Circuit Design in VHDL: BCD Counter Design and implementation on ZedBoard

  5. Implementing digital design lab on Xilinx Zynq Boards: ZedBoard and Zybo

  6. Structural Design in VHDL: Creating Full Adder using Half Adder

  7. State Machine Design : Designing Sequence Detector in VHDL

  8. 8-bit ALU Design and Simulation in VHDL

Content

Section 1_Introduction and Overview of VHDL, VIVADO & Zynq

Introduction and Overview of VHDL
VHDL Data Types and Operators:Overview with How to create user defined data type
Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License
Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard
Nor Gate Implementation on ZedBoard FPGA (Optional)

Simulating VHDL code with Testbench

Simulation Overview and Lab: Simulation of NAND Gate in VIVADO

Conditional Statements in VHDL

Lecture: Conditional Statement in VHDL
Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard
Section 3_3 Lab 31 Decoder Demo

Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO

Section 4_1 Combinational Circuit Design in VHDL
Section 4_2 Lab41 Half Adder Design and Implementation with VIVADO and Zynq
Half Adder Implementation on ZedBoard: Demo

Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL

Seven Segment Decoder Design in VHDL

Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)

Section 5 Structural Design with VHDL with Lab on Designing Full Adder using Hal
Section 5 Lab 51 Structural Design Lab for Full Adder Demo

Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL

Section 6_1 Sequential Circuit Design in VHDL
Section 6_2 Lab 61 BCD Counter Design and Implementation
BCD Counter Implementation on ZedBoard: Demo

Section 7 Finite State Machine Design:Sequence Detector Design/Implement in VHDL

Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design

ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)

ALU Design (ALU Overview and 8 Bit ALU Design)-I
ALU Design (ALU Overview and 8 Bit ALU Design)-II
ALU Design: Lab 81 N bit ALU Design

VHDL Reference Guide (From Basic Design to FSM Examples) from Digitronix Nepal

VHDL Reference Guide from Digitronix Nepal (Basic Gate to Sequential Circuits)

Bonus Lecture

What Next?
Books and Reference Links

Screenshots

Xilinx VIVADO Beginner Course for FPGA Development in VHDL - Screenshot_01Xilinx VIVADO Beginner Course for FPGA Development in VHDL - Screenshot_02Xilinx VIVADO Beginner Course for FPGA Development in VHDL - Screenshot_03Xilinx VIVADO Beginner Course for FPGA Development in VHDL - Screenshot_04

Reviews

Simon
April 17, 2018
I'm not convinced the presenter is using their own slides. They skip back and forwards, they skip slides ahead then back and ... while still discussing a slide. They just skip slides. The frequency of "umm" and dead air is also not great.
Nives
October 17, 2017
The content of the lectures is good, but it's often hard to understand the lecturer because he talks faster or a bit incomprehensible.

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1138728
udemy ID
3/8/2017
course created date
11/22/2019
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