High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

Logic Design with Vitis-HLS

4.60 (132 reviews)
Udemy
platform
English
language
Hardware
category
Mohammad Hosseinbady
instructor
High-Level Synthesis for FPGA, Part 2 - Sequential Circuits
1,761
students
9.5 hours
content
Mar 2023
last update
$79.99
regular price

What you will learn

Designing sequential logic circuits with C/C++ language using the HLS approach

Understanding the basic concepts of High-Level Synthesis (HLS)

Using HLS concepts for designing sequential logic circuits

HLS design flow for FPGAs

Working with Xilinx Vitis-HLS and Vivado design suite Toolsets

How to generate RTL hardware IPs using Vitis-HLS

Writing C-testbench in HLS

Implementing three exciting projects with HLS

Why take this course?

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.

This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.

This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Content

Prologue

Introduction
Course Structure

HW/SW Setup

Introduction
Vivado-HLX
Vivado and Vitis-HLS
Install Vivado HLx
Test Installation

D Flip-Flop (DFF)

Introduction
Memory Cell
Sequential Circuits
Clock Signal
State Concept
Reset Signal
Register
DFF LAB01
DFF LAB02
Exercises

Single Cycle Design Flow

Introduction
Definition and Idea
Parallel to Serial
Serial to Parallel
IP-Centric Design Flow
Parallel-Serial-Parallel LAB
Exercises

Testbench 01

Introduction
Definition
Parallel to Serial Testbench
Serial to Parallel Testbench
Input Waveform
Exercises

State Machine

Introduction
Definition
Concepts
Template
Combination Lock-VitisHLS
CombinationLock-Vivado
Exercises

Utilities

Introduction
Timer
Debouncer
Counter
Clock Generator
Pulse Generator
Single-Cycle Regular Pulses
Edge Detector
Exercises

Vending Machine

Introduction
Definition
Vitis-HLS
Vivado
Exercises

Integrated Logic Analyzer (ILA)

Introduction
Definition
Vivado
Exercises

Function Pipelining

Introduction
Definition
Multi-Cycle Design
Pipeline Design
Performance Metrics
IIR Example
Exercises

Seven Segments

Introduction
Definition
7Segment Driver
7Segment HLS
7Segment Vivado
Four-Digit Counter
Exercises

PMOD

Introduction
Definition
PMOD LED
PMOD Keyboard
Exercises

Interface Synthesis

Introduction
SCII Proc&Cons
Definition
Interface Synthesis
Block Level ap_ctrl_hs
Block Level ap_ctrl_hs: vitis-hls
Port Level ap_vld
Port Level ap_ack
Port Level ap_hs
Exercises

Project 1: Digital Dice

Introduction
Definition
Counter Based
LFSR
Exercises

Project 2: UART

Introduction
Definition
Design Structure and HLS
Transmitter-VitisHLS+Vivado
Receiver-VitisHLS+Vivado
Exercises

Project 3: Stepper Motor

Introduction
Definition
One-Phase-On: Vitis-HLS
Two-Phase-On: Vitis-HLS
Two-Phase-On with Control: Vitis-HLS
One&Two-Phase-On (Half Step): Vitis-HLS
Exercises

Screenshots

High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_01High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_02High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_03High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_04

Reviews

Dan
January 18, 2023
The overall content and structure is good. Some lectures should probably be combined to increase the pace and to remove redundant information. I'm not a fan of "we're going to get to that in the next lecture" when both lectures are only a couple of minutes long.
Sayedakbar
January 26, 2022
The best. Very instructive, structured, theoretical and complete, exactly what I was looking for. That's why I bought the whole series and Function Acceleration as well. This course is very well structured. The slides are very clear, specially take away messages. You can follow the instructor without any problem. Looking forward to the next series of courses. حاجی پرجم ت بالاس
Mustafa
December 29, 2021
extremely helpful course to understand digital design methodologies explanations are clear. more interface types ,more optimization chapters could be better.
Juan
May 11, 2021
An excellent course on the sequential aspects of FPGA-based digital implementations, highly recommended.

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Related Topics

FPGA
3639976
udemy ID
11/17/2020
course created date
3/30/2021
course indexed date
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