Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Create Verilog and C codes for implementing the AXI4 bus protocol on ZYNQ FPGA

4.25 (137 reviews)

Udemy

platform

English

language

Hardware

What you will learn

Use Xilinx AXI4-based IP Cores

Create your own AXI4-based IP Cores from scratch

Create an AXI4-based Hardware Accelerator IP Core (GCD case study)

Create an AXI4-based Transceiver IP Core (UART case study)

Why take this course?

Note: Take this course if you want save money in training costs of similar contents. The Official Xilinx Traning Courses cost typically from 600 USD to 4000 USD. This course is not only teaches the Zynq Processing System (PS) but also the Programmable Logic (FPGA), and the interface between them.

Published (20 Apr 2019): The GCD accelerator and UART sections will be added later, and the course price will be increased, when those sections are added.

Update 1 (22 Apr 2019): English Subtitles/CCs are enabled for this course

Update 2 (02 Jan 2020): Add bonus lecture.

What is AXI?

Advanced eXtensible Interface (AXI) is an industry-standard, system bus for the connection between CPU and peripheral in System-on-Chip (SoC) design. Today AXI version 4 (AXI4) is used in many SoC that use ARM Cortex-A processors, such as Qualcomm Snapdragon, Samsung Exynos, Broadcom (used on Raspberry Pi), and many more.

What is ZYNQ?
ZYNQ is actually a SoC, not just a FPGA, because ZYNQ consists of hard processor system (ARM Cortex-A9) and programmable logic (Xilinx 7-series FPGA, equivalent to Artix-7 FPGA). The ZYNQ device enables the implementation of custom logic such as hardware accelerator in combination with software that runs on the ARM Cortex-A9. ZYNQ can also run Linux OS, which makes this device like the popular Raspberry Pi, but with FPGA inside.

This course is based on hands-on laboratory with a lot of examples. Sample codes are provided for every project in this courses.

You will receive a certificate of completion when finishing this course. There is also Udemy 30 Day Money Back Guarantee, if you are not satisfied with this course.

So, click the course button and see you inside the course.

Reviews

Gangamma

December 29, 2021

good introduction to axi interface in verilog.Codes are tested first in test bench then on board using SDK. Thank you

Dave

September 15, 2021

The instructors' English is very broken and difficult to understand. However, the closed-captioning apparently was corrected and much appreciated. The instructor appears to have a good understanding of the AXI interface and the labs are helpful. Unfortunately, the version of Vivado is a bit behind (2016) as is the development board (Zybo) so the use of Vitis is not used and that would be a good addition for future course updates. I am progressing through the course (presently on section 3) and will continue to augment this review.

Rakesh

September 7, 2021

Learned a lot. I was expecting content where in Xilinx Wrappers are used for axi bus rather than handcoding axi bus every now and then

Mustafa

February 4, 2021

Pronunciation would be better. Examples are good to learn copy+past for the codes are not helpful to understand how it is developed, at least the Finite State Machine of the IP could be mentioned.

Matthias

December 21, 2020

I learned a lot from this course. It would be the perfect course to get knowledge about AXI-Bus, if following changes would be done: - Add a third part and small project for AXI-non-Lite - Instead of adding the code for the modules as a whole bunch it should be added in small parts with a bit more detailed explanations because the projects in this course course are very advanced for beginners of Zynq and Vivado - Ideally the Code would be offered as both a VHDL version and a Verilog one Greetings

306

May 26, 2020

This is very detailed course on the AXI Protocol. There are lots of examples that are very helpful: design, simulation, debug using the XSCT, and detailed slides. Well worth the money.

Wing

December 11, 2019

Instructor's accent was very difficult to understand at times. Half of examples don't work in the latest 2019.x Vivado tools because xdb is no longer available and the supplementary intructions for xsct also don't work. The last section on an so-called AXI "stream" interface example is pointless, because he doesn't interface it directly to the Zynq -- if you need to instantiate (not one, but two!) AXI-Lite peripherals to talk with an AXI-stream peripheral, you've already negated all the benefits of implementing an AXI-stream peripheral!

Triston

October 19, 2019

It seems a bit off that one has to go into the wrapper to get the pin names, and then copy this in the constraint file. In fact, I've done other tutorials where this isn't done. It was a nice "dive," but this just seems to add detail that isn't needed. we're just adding outputs and inputs.

Bilal

May 18, 2019

Your lectures are Good. I am wondering if you can also prepare a course on ZYBO-USB and ZYBO-Ethernet interface ?

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