FPGA Embedded Design, Part 4 - Microprocessor Design

Learn FPGA embedded application design starting with the basics and leaving with your own CPU.

4.10 (103 reviews)
Udemy
platform
English
language
Hardware
category
1,194
students
5.5 hours
content
Jan 2022
last update
$64.99
regular price

What you will learn

How a CPU works.

How to design a CPU core of your own.

How to design an Instruction Set Architecture

How to design a CPU core in Verilog.

How to synthesize a CPU core for Altera and Xilinx FPGAs.

Description

It's time to take on a Challenge! How does designing a CPU sound?

In this fourth part of the FPGA Embedded Design series, we'll design a CPU from scratch to finally get it up and running on several platforms.

We'll write most of the code in the Vivado Design Suite, but you'll have the chance to see it working as well in Quartus Prime, EDA Playground or LabsLand, so you can follow along with your favorite tools. The FPGA boards we'll use are the BASYS3, by Digilent (with a Xilinx FPGA), and the DE0-CV from Terasic (with an Intel FPGA).

This course consists of three main parts:

  1. Foundations of Computer Architecture, where we'll cover the essentials of CPU design and jargon.

  2. Design of our own CPU, where we'll make several design decisions to come up with a soft processor that meets our needs.

  3. Hands-On Development, where we'll write the code, simulate and finally get our CPU into an FPGA board. No purchases are required for this part, but it sure helps to have your own board to follow along, and keep on tinkering in the future with your new soft processor.

What are you waiting for? Let's have fun designing a CPU!!! 

Content

Introduction

Introduction
Instructor Introduction
Motivation 1
Motivation 2
Motivation 3

A Crash Course on Computer Architecture

Parts of a Microprocessor-Based System
Why we need a Bus Architecture
The Bus Architecture
The Data Bus
The Address Bus
The Control Bus
How is it possible to drive a bus?
The Memory Subsystem
The Input/Output Subsystem

Inside the CPU

Parts of a CPU
Arithmetic Logic Unit
Registers
Special Registers
The Data Path
Control Logic
Instruction Encoding
Instruction Execution

Some Design Approaches

CPU Design Criteria
Structural vs. Behavioral Approaches
Instruction Set Architecture
Addressing Modes
Some Addressing Mode Examples
Number of Operands per Instruction
CISC vs RISC Architectures
Harvard vs. Von Neumann

Let's Design a CPU!

Program 1: Add Two Numbers
A Quick and Dirty Approach
Program 3: Calculate a Factorial
Program 2: Fibonacci Sequence
The Instructions we Need
Your Personal Preferences
Really, make your own choices!
How many operands per instruction?
CISC or RISC?
Harvard or Von Neumann?
System Design
CPU Registers
Memory Model
Input/Output Model

Instruction Set Design

Instruction Set Design
Instruction Encoding Spreadsheet
Instruction Set Encoding
Assembly Code for Program Example #1 (Adding Two Numbers)
Assembly Code for Program Example #2 (Fibonacci Number)
Assembly Code for Program Example #3 (Factorial)
A Review of Addressing Modes
A Review of Used Instructions
Room for Growth

Writing Our Own CPU RTL Code

Wiring your CPU RTL Code
A bit of RTL and lots of Behavioral Code
Registers
State Machine Design
Vivado Code
The states of Jimmy
The Opcodes
Extracting the Opcode from the Instruction
The Fetch Cycle

Instruction Set Implementation

Instruction Set Implementation
Implementing the Instructions
Addition
Multiplication
Update on MUL
Register Transfer
No Operation
Load Immediate
Compare Immediate
Decrement
Port Input
Port Output
Unconditional Branching
Branch if Higher
Branch on Equal

System Design

System Design
Finishing up the System
Coding in our own Machine Language
Writing the Program Memory RTL
Writing the Example Program #1 in our Memory
Writing the Example Program #2 in our Memory
Writing the Example Program #3 in our Memory

Synthesis and Simulation

A word on Synthesis
Simulated Hardware for Program #1
Simulated Hardware for Programs #2 and #3
Vivado Simulation for Program #1
Vivado Simulation for Program #2
Vivado Simulation for Program #3
Quartus Code
Quartus Simulation for Program #1
Quartus Simulation for Program #2
Quartus Simulation for Program #3

Fun with EDA Playground

Fun with EDA Playground
EDAPlayground Simulation for Program #1
EDAPlayground Simulation for Program #2
EDAPlayground Simulation for Program #3

Target Hardware: BASYS3 by Xilinx and Digilent

The Target FPGA Matters
The Hardware in the BASYS3 Board
BASYS3 Testing Hardware for Program 1
BASYS3 Testing Hardware for Programs 2 and 3
Vivado Code for Program 1
Vivado Code for Programs 2 and 3
Vivado Schematics
BASYS3 Live Demo: Program 1
BASYS3 Live Demo: Program 2
BASYS3 Live Demo: Program 3

Target Hardware: The DE0-CV Board, by Terasic and Intel

DE0-CV Hardware
DE0-CV Testing Hardware for Example Programs
Quartus Code for Program 1
Quartus Code for Programs 2 and 3
DE0-CV Live Demo: Program 1
DE0-CV Live Demo: Program 3

Fun with LabsLand

LabsLand Code
LabsLand Live Demo: Program 1
LabsLand Live Demo: Program 2
LabsLand Live Demo: Program 3

It's your Turn to Tweak the Code!

Now it's your turn to tweak the code!
Some Changes Here and There
Implement Variables with Load and Store Direct
Implement Arrays with Load and Store Indirect
Implement the Compare Instruction Between Registers
Implement a Stack with Push and Pop
Implement Subroutines with BSR and RET

Wrap Up

Think of all the things we learned!
What's Next
Farewell
Bonus Lecture: LabsLand and more from Closure Labs!

Screenshots

FPGA Embedded Design, Part 4 - Microprocessor Design - Screenshot_01FPGA Embedded Design, Part 4 - Microprocessor Design - Screenshot_02FPGA Embedded Design, Part 4 - Microprocessor Design - Screenshot_03FPGA Embedded Design, Part 4 - Microprocessor Design - Screenshot_04

Reviews

Jim
May 3, 2023
In order to understand the content and follow along one should have a good fundamental knowledge of digital design and computer architecture, otherwise, you would get lost as many concepts are not thoroughly explained. The section that details the prerequisites is misleading. So, in my opinion, this course is primarily for those who know about the background theory of digital systems and just want to design a CPU. My advice would be to learn digital logic and computer architecture first and then come here to put into practice the knowledge you acquired.
Ethan
January 27, 2023
I set out to learn how to implement a CPU on FPGA to prepare for my Computer Architecture class. This class gives me great hands-on skills to complete my class assignments. As a high school junior, I find the material very clearly explained. Thank you, Ethan Le
Brian
November 15, 2022
There was a lot of good information packed into this course. Eduardo is a very good presenter of technical information. Thumbs up!!
Timothy
March 16, 2022
Very clear and engaging videos. Nice and short and focused. Really cool and exciting to be able to create your own CPU in an FPGA.
Michael
December 23, 2021
The instructor is very knowledgeable and shares concise, real world experience and examples throughout. He also has made this subject matter easy to understand, despite complex areas covered. His approach is excellent!
Daniel
February 4, 2021
It was a good match, but I feel like there should be an extra chapter to really describe how difficult it is to extend a soft processor
Ishan
January 27, 2021
Would like to thank the Instructor. This course really helped me out to understand the design implementation of a microcomputer. Regards Ishan Sakhuja
Hari
June 18, 2020
Well prepared course, but I have to say I was expecting to be able to code with very basic skeleton versions of the code and progress to the final "product". But now it looks like we are downloading the finished project, and just following along with the video on how it progressed from start to finish. So will not have any personal experience of how to develop and test each stage of such a project myself...

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udemy ID
6/6/2017
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7/24/2020
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