Introduction
Introduction
Instructor Introduction
Motivation 1
Motivation 2
Motivation 3
A Crash Course on Computer Architecture
Parts of a Microprocessor-Based System
Why we need a Bus Architecture
The Bus Architecture
The Data Bus
The Address Bus
The Control Bus
How is it possible to drive a bus?
The Memory Subsystem
The Input/Output Subsystem
Inside the CPU
Parts of a CPU
Arithmetic Logic Unit
Registers
Special Registers
The Data Path
Control Logic
Instruction Encoding
Instruction Execution
Some Design Approaches
CPU Design Criteria
Structural vs. Behavioral Approaches
Instruction Set Architecture
Addressing Modes
Some Addressing Mode Examples
Number of Operands per Instruction
CISC vs RISC Architectures
Harvard vs. Von Neumann
Let's Design a CPU!
Program 1: Add Two Numbers
A Quick and Dirty Approach
Program 3: Calculate a Factorial
Program 2: Fibonacci Sequence
The Instructions we Need
Your Personal Preferences
Really, make your own choices!
How many operands per instruction?
CISC or RISC?
Harvard or Von Neumann?
System Design
CPU Registers
Memory Model
Input/Output Model
Instruction Set Design
Instruction Set Design
Instruction Encoding Spreadsheet
Instruction Set Encoding
Assembly Code for Program Example #1 (Adding Two Numbers)
Assembly Code for Program Example #2 (Fibonacci Number)
Assembly Code for Program Example #3 (Factorial)
A Review of Addressing Modes
A Review of Used Instructions
Room for Growth
Writing Our Own CPU RTL Code
Wiring your CPU RTL Code
A bit of RTL and lots of Behavioral Code
Registers
State Machine Design
Vivado Code
The states of Jimmy
The Opcodes
Extracting the Opcode from the Instruction
The Fetch Cycle
Instruction Set Implementation
Instruction Set Implementation
Implementing the Instructions
Addition
Multiplication
Update on MUL
Register Transfer
No Operation
Load Immediate
Compare Immediate
Decrement
Port Input
Port Output
Unconditional Branching
Branch if Higher
Branch on Equal
System Design
System Design
Finishing up the System
Coding in our own Machine Language
Writing the Program Memory RTL
Writing the Example Program #1 in our Memory
Writing the Example Program #2 in our Memory
Writing the Example Program #3 in our Memory
Synthesis and Simulation
A word on Synthesis
Simulated Hardware for Program #1
Simulated Hardware for Programs #2 and #3
Vivado Simulation for Program #1
Vivado Simulation for Program #2
Vivado Simulation for Program #3
Quartus Code
Quartus Simulation for Program #1
Quartus Simulation for Program #2
Quartus Simulation for Program #3
Fun with EDA Playground
Fun with EDA Playground
EDAPlayground Simulation for Program #1
EDAPlayground Simulation for Program #2
EDAPlayground Simulation for Program #3
Target Hardware: BASYS3 by Xilinx and Digilent
The Target FPGA Matters
The Hardware in the BASYS3 Board
BASYS3 Testing Hardware for Program 1
BASYS3 Testing Hardware for Programs 2 and 3
Vivado Code for Program 1
Vivado Code for Programs 2 and 3
Vivado Schematics
BASYS3 Live Demo: Program 1
BASYS3 Live Demo: Program 2
BASYS3 Live Demo: Program 3
Target Hardware: The DE0-CV Board, by Terasic and Intel
DE0-CV Hardware
DE0-CV Testing Hardware for Example Programs
Quartus Code for Program 1
Quartus Code for Programs 2 and 3
DE0-CV Live Demo: Program 1
DE0-CV Live Demo: Program 3
Fun with LabsLand
LabsLand Code
LabsLand Live Demo: Program 1
LabsLand Live Demo: Program 2
LabsLand Live Demo: Program 3
It's your Turn to Tweak the Code!
Now it's your turn to tweak the code!
Some Changes Here and There
Implement Variables with Load and Store Direct
Implement Arrays with Load and Store Indirect
Implement the Compare Instruction Between Registers
Implement a Stack with Push and Pop
Implement Subroutines with BSR and RET
Wrap Up
Think of all the things we learned!
What's Next
Farewell
Bonus Lecture: LabsLand and more from Closure Labs!