FPGA Design with VIVADO HLS -High Level Synthesis

Design, Simulate, Synthesize & Export IP with VIVADO HLS : An FPGA Design Approach with C/C++

3.25 (94 reviews)

Udemy

platform

English

language

Hardware

What you will learn

Vitis HLS Installation, OpenCV Setup and LAB session

Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS

Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA

Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA

Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)

Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool

Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA

Why take this course?

🌟 Course Title: FPGA Design with VIVADO HLS - High Level Synthesis 🌟

Course Headline:

Design, Simulate, Synthesize & Export IP with VIVADO HLS: An FPGA Design Approach with C/C++ 🚀

Course Description:

As an added bonus, this course also guides you through the installation of Vitis HLS, setting up OpenCV in Vitis HLS, and performing examples using the Vitis Vision 2020.2 tool.

Embark on a comprehensive learning journey where you'll master FPGA design by leveraging the power of C/C++ programming. This course is tailored for beginners to advanced learners who wish to transition from basic High Level Synthesis (HLS) Design & C-Simulation to designing complex computer vision applications, such as Real Time Sobel Edge Detection.

🔹 Key Coverage:

Creating a new project on HLS
Running C Simulation on HLS
Synthesizing the HLS Project's to convert C/C++ source code into Verilog/VHDL and SystemC for efficient hardware implementation.
Performing C/RTL Co-simulation to validate your designs at a higher abstraction level, saving time and resources.
Exporting HLS Designs into an IP core format compatible with VIVADO IP Integrator.
A dedicated session on designing Sobel Edge Detection IP in HLS, including its exportation to the VIVADO tool and implementation on a Zybo FPGA for real-world application.

By enrolling in this course, you will gain hands-on experience with:

Designing complex systems using C/C++.
Simulating your designs at a high level.
Synthesizing your high-level designs into efficient hardware implementations.
Implementing and exporting your HLS projects for practical applications.

What to Expect: After completing this course, you will be fully equipped to design, simulate, synthesize, and implement or export HLS projects. You'll understand how to utilize the extensive C/C++ libraries provided by HLS for computer vision (like OpenCV), video/image processing, and complex mathematical computations. These are areas that are notoriously challenging when implemented directly in hardware description languages (HDL) or at the register-transfer level (RTL).

Lab Work:

In this interactive lab, you will apply your newly acquired skills by designing, simulating, synthesizing, and implementing a variety of projects using C++. You will work on:

Designing a Counter to understand basic counting operations.
Simulating a Matrix Multiplier to handle matrix computations.
Frequency Modulator design to generate signals with varying frequency characteristics.
Numerically Controlled Oscillator (NCO Design) to create precise oscillations for digital signal processing tasks.

Additionally, you will integrate the exported HLS projects with the Zynq Processing System within VIVADO IP Integrator and proceed to synthesize and implement your designs on a Xilinx Zynq SoC using VIVADO IPI.

Join us for an enriching learning experience that combines theoretical knowledge with practical, real-world applications in FPGA design using VIVADO HLS! 🛠️💻✨

Screenshots

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Our review

🌟 Overall Course Rating: 3.40/5

Course Review

Pros:

Comprehensive Example Projects: The course provides several example projects with the required materials, which are essential for understanding the practical application of the concepts taught.
Responsive Instructor: The instructor is responsive to questions related to the course, offering good follow-up and support.
Slides and Visual Aids: Thanks to the instructor for providing helpful slides that aid in learning.
Real-World Application: The course shows an actual project from beginning to end, giving students a clear view of the flow of a project and the big picture.

Cons:

Audio Quality Issues: There are complaints about the audio quality in some videos, with suggestions for using voice editing tools to improve clarity. Additionally, one video loses audio after approximately 50% of its duration.
Video Pace and Clarity: Some students find the instructor's pace very rapid and difficult to follow. There is a request for the ability to slow down the video playback. Subtitles are also missing, which would greatly assist those who have difficulty understanding the instructor's English accent.
Content Clarity and Structure: The course content is described as confusing and disorganized. There are open-ended questions and a lack of clarity in how codes are presented. The course leaves many things to be addressed "for another moment," which can be frustrating for learners looking for concrete instructions.
Engagement with Topics: Some sections, particularly section 3, could benefit from slower pacing and clearer explanations, especially in the FIR example where the zipped files provided did not match the HLS project shown in the video.
Lack of In-Depth Coverage: The course skims over topics without going into depth, particularly on different Input/Output (IO) types, optimization techniques, and how to use exported RTL cores in a Vivado platform.
Outdated Material: There are concerns that the course content is based on an older version of Vivado (prior to the launch of Vitis), making it misleading as the course name includes "Vitis." This results in a waste of time for students expecting up-to-date material on Vitis.
Technical Issues: Students report poor English, annoying background noises, and wasted time waiting for compilers and synthesizers to run without any valuable follow-up on how to manage this time effectively.
Instructor's Expertise: There are concerns that the instructor uses engineering topics as examples but does not fully understand them. This could lead to misconceptions or incomplete understanding of the material.

Final Thoughts:

While there are aspects of the course that are well-received, such as the provision of comprehensive materials and the instructor's responsiveness, several significant issues arise regarding content clarity, audio quality, pacing, and relevance to current technology (Vitis). These concerns impact the overall learning experience and effectiveness of the course. A potential follow-up course focusing on HLS with Vivado and addressing the current shortcomings would likely be of great interest to students. It is recommended that these issues be addressed in future iterations of the course to improve both engagement and educational value.