Develop and analyze a SIMULINK model from scratch
Live model development and analysis from hand-written requirements made for beginners
4.17 (3 reviews)
160
students
6 hours
content
Nov 2020
last update
$34.99
regular price
What you will learn
Capture a set of raw requirements and make a design flow diagram for a timer.
Select the SIMULINK blocks required for the design and start developing the model from scratch.
Identify and analyze potential pitfalls in the model and fix bugs.
Learn some of useful concepts and features of SIMULINK as we go.
Why take this course?
This course uses a basic timer logic to get you started with model development. It has been made in the form of a live development session.
The lectures are continuous in nature which traverses through basic stages of requirements capture, design flow diagram, model development, analysis and testing.
Occasionally important lecture notes are shown in-lecture in the form of Messages. Also every lecture ends with a slide-based brief review where key take-aways from the lecture are shown.
Content
REQUIREMENTS AND DESIGN
WE NEED A TIMER
TIMER REQUIREMENTS - DIAGRAM
TIMER REQUIREMENTS - DESCRIPTIVE
FLOW DIAGRAM
FLOW DIAGRAM - CONTINUED
MODELING AND ANALYSIS
SELECT THE SIMULINK BLOCKS
TIMER TRIGGER CONDITION SWITCH
DESIGN ANALYSIS FOR TIMER INC
TIMER MAX CONDITION
CREATE TEST MODEL
ALGEBRAIC LOOP
ALGEBRAIC LOOP SIMPLE TEST
ANALYZE THE SIMPLE ALGEBRAIC LOOP
SIMULATION AND ANALYSIS
SIMULATE THE ALGEBRAIC LOOP MODEL
EXECUTION ORDER
SIMULATION STEPPER CONFIGURATION
USE THE SIMULATION STEPPER
BREAK THE ALGEBRAIC LOOP
CAPTURE EXPECTED DATA
EXPECTED DATA - MORE TIME STEPS
SIMULATE THE BROKEN ALGEBRAIC LOOP
SIMULATE AND VERIFY
VERIFY USING SIMULATION STEPPER
VERIFY TIMER STATUS CHANGE
VERIFY USING SIGNAL LOGS
VARY TIMER MAX AND SIMULATE
FIX FOR FLOATING POINT BUG
VERIFY WITH TIMER TOLERANCE
PLACING THE DELAY BLOCK
TIMER SUBSYSTEM
DELAY THE SINE WAVE USING TIMER
SOLVER TYPES
VARIABLE STEP SOLVER
FIXED STEP SOLVER
CHOOSING THE SOLVER TYPE
VERIFY VARIABLE STEP TIME LOGS
VERIFY USING FIXED STEP SOLVER
SAMPLE TIMES
DISCRETE SAMPLE TIME
INHERITED AND CONSTANT SAMPLE TIME
SAMPLE TIME VISUAL CHECK
COMPILED SAMPLE TIME OF BLOCKS
RISING EDGE TIMER
SUBSYSTEM REFERENCE
USE SUBSYSTEM REFERENCE FOR TIMER
DESIGN RISING EDGE DETECT LOGIC
RISING EDGE DETECT IN MODEL
DEPLOY RISING EDGE DETECT FOR TIMER
VERIFY RISING EDGE TIMER
PROVE SINE PROPERTY OBSERVED
MISCELLANEOUS
DATA EXPORT FORMAT CHANGE
VIEWMARKS
EXECUTION ORDER FOR SUBSYSTEM
ANNOTATIONS
Screenshots
Charts
Price
Rating
Enrollment distribution
3466206
udemy ID
9/1/2020
course created date
10/28/2022
course indexed date
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