AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog

Explanation of AMBA AXI protocol based on Xilinx Infrastructure, verilog and System verilog

4.00 (148 reviews)

Udemy

platform

English

language

Hardware

What you will learn

ARM AXI Protocol

Xilinx AXI Infrastructure

Xilinx Vivado Tool

FPGA and Verilog

Zynq

System Verilog

Why take this course?

Why AXI?

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The answer is simple - there is NO any Soc or complex system, which does not contain AXI. If your work somehow is connected with processor, controller or any other big system than there will be multiple AXI buses in the system. AXI bus is a ARM standard bus, which is supported by all hardware companies e.g. Xilinx, Intel, AMD and so on. And by the advance of AI the AXI is going to be more and more popular.

In this course AXI protocol and its sub-parts will be explained.

Also as a free side knowledge you will study Vivado with its IPs, simulation methods and many more.

Target Students

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The course is mainly targeted for FPGA designers, who are using AXI based modules in the design. Also the course will be useful for engineers who is starting to use AXI protocol.

The course is extremely helpful for graduate students who is looking for a new job as a FPGA or Soc Developer, in my previous 3 companies AXI questions were the most often to ask the fresh graduates for hire.

Course Content

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In the course mainly the basics of AXI protocol family is explained, which allows students easily understand and use AXI based IPs. This is more practical view of AXI usage allowing for jump start to use AXI based modules. The course does not go to FPGA board level,as the target is AXI protocol and Xilinx provided AXI Infrastucture understanding.The course concentrated on simulation level, not FPGA board running is done.

The AXI protocol is complex enough and sometimes it takes much time to get used to it. Usually the AXI protocol is easy to understand when you are familiar with much easy version of it, which are AXI-Stream and AXI-Lite. The course is based on bottom-up-style. At first I explain AXI-stream protocol, than explain AXI-Lite protocol in detail. We do both of these protocol designs using Verilog.

Than having all that baggage of knowledge we move to AXI protocol.

In the course I tried to review the ARM speck for AXI, hoping that this will help students easily jump in speck reading, after finishing the course.

Special Thanks:

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I want to express special thanks to Eduard Vardanyan, from ARM, for his great support in making this course. His profound experience and deep knowledge helped me to explain complex AXI parts simply. Without his help I could not do this.

Caution:

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Also I apologize for my English, I tried my best to speak clearly and grammatically correct, however sometimes there are some mistakes. I really hope that my non-native English will not bother students to understand the material.

Course Materials:

===============

All course codes can be downloaded from Github.

Note: If you have software background, I would suggest little bit become familiar with Verilog. There are several lectures which require Verilog and hardware basics.

Screenshots

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog - Screenshot_01

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog - Screenshot_02

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog - Screenshot_03

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog - Screenshot_04

Reviews

Sudeshna

March 16, 2023

Lots of error and the course material is not updated even after many feedbacks. Final project does not have much more than just the vivado example project which is already available from xilinx. Many students asked for the sample TB for the final project but it is not provided. Otherwise the explanation of AXI protocol is thorough and good. When comes to actual implementation part many details are missing.

Jason

November 4, 2022

Exactly the level of content that I wanted. As an embedded software engineer working for the first time with hardware acceleration the examples in Vivado were particularly appreciated. Code is often easier for me to understand than words! Hayk, I appreciated your up-front warning about English being a second language, my ears soon got attuned to your accent and delivery and it hasn't, for me, detracted at all from the excellent content.

Aayush

January 15, 2022

The course is almost upto the expectation. However, along with simple master and slave design, if you could teach us to design master and slave for some particular use case, that would have been amazing

Abhav

December 3, 2020

As a beginner I was able to clearly understand the protocols The course is systematically designed for easy understanding and progresses in a systematic manner .

306

June 2, 2020

This is a very good course on AXI. The instructor generated a lot of documentation that helps understanding the AXI-Lite Protocol, AXI Burst Operations, AXI Stream FIFO, and AXI Traffic Generator. I was able to do all the examples except the the final project on the AXI RAM Write & Read Project using the AXI Traffic Generator. My only suggestion would be when doing the examples show each step in building the example and simulating it. Then you get the people who are beginners with Vivado and also the people wanting to learn AXI. Over all money well spent.

Kaushik

April 6, 2020

So far, so good. The instructor has given a clear idea of the fundamentals of the class. Thank you so much!

Mourya

April 2, 2020

when you don't know anything about the AXI protocol then this is the good place to start . Instructor also clarify our doubts in a understandable manner

Frank

March 30, 2020

Just Great! Took this course, while isolated at home. The course covers everything about AXI family, including Xlinx FPGAs. And the final project makes your knowledge very practical.

Anam

October 22, 2019

He is not explaining clearly he is jumping immediately to other topic if he don’t know about thatand he should explain properly

Reggie

July 11, 2019

Excellent explanations. Instructor has a firm understanding of the material and easily conveys that.

Mark

June 22, 2019

The course is very helpful!! Thank you for creating such an informative course. It explains everything about AXI family, in a very easy and systematic way. Absolutely recommended for someone who wants to know AXI. The only think that lack in the course is Zynq part, AXI is widely used in Zynq. And would be nice to have some lectures related to Zynq.

Eduard

March 30, 2019

Hayk explains the main aspects of AXI protocol and gives essential information necessary to understand AXI functionality.

Tom

March 26, 2019

Excellent!!! This course explains everything you need to know about AXI family! Lecturer explains very detail the AXI protocol with its sub-protocols such has AXI-Stream and Lite. And course structure is made such a smart way that until you reach to AXI section you already know it! The final project is also very helpful, real life project which can be used in own purposes. The thing which miss in the course is there is no C codes, explaining how to work with AXI using C. But knowing the protocol it is easy to do it, it took 1 hour from me to use AXI with C. Also if you dont have Vivado, I recommend download as it is FREE.

Mayur

March 25, 2019

This is a great course for those who want to learn communication protocols using Verilog/SV. English communication could be improved but that doesn't create any obstacle in learning process. Thank you.

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